library ieee;
use ieee.std_logic_1164.all;

entity testbench_shift_reg_n is
end testbench_shift_reg_n;

architecture test of testbench_shift_reg_n is

	constant N : integer := 8;

	component shift_reg_n
		generic (
			N : integer
		);
		port (
			d_i     : in  std_logic_vector(N-1 downto 0);
			si_i    : in  std_logic;
			l_i     : in  std_logic;
			nclk_i  : in  std_logic;
			so_o    : out std_logic;
			q_o     : out std_logic_vector(N-1 downto 0)
		);
	end component;

	signal d     : std_logic_vector(N-1 downto 0);
	signal si    : std_logic;
	signal l     : std_logic;
	signal nclk  : std_logic;
	signal so    : std_logic;
	signal q     : std_logic_vector(N-1 downto 0);

begin

	shift_reg_n_inst : shift_reg_n generic map (
		N 		=> N
	) port map (
		d_i     => d, 
		si_i    => si,
		l_i     => l,
		nclk_i  => nclk,
		so_o    => so,
		q_o     => q
	);

	gen_clk : process
	begin
		nclk <= '0';
		wait for 10 ns;
		nclk <= '1';
		wait for 10 ns;
	end process;

	gen_test : process
	begin

		wait for 90 ns;

		d     <= X"C0"; 
		si    <= '1';
		l     <= '1';

		wait for 20 ns;

		si    <= '1';
		l     <= '0';

		wait for 20 ns;

		si    <= '0';
		l     <= '0';

		wait;
	end process;

end test;
